Modern digital logic devices offer unprecedented performance. For a variety of digital ICs, speed, level of integration (i.e., transistor density) and capabilities have improved. Moreover, in many cases, these performance improvements have been accompanied by reductions in size, power consumption and cost of the devices. However, these benefits have required greater complexity in digital logic design. Because of this complexity, the investment of time and resources by the manufacturer to design and fabricate a digital logic device has increased. For this same reason, the possibility of a mistake or oversight on the part of the designer has become more likely, and costlier to correct.
As digital logic devices have continued to evolve, hierarchical design techniques have become valuable as an approach for managing their complexity. At each hierarchical level, logic elements are formed from combinations of simpler elements. At the lowest hierarchical level of the design, the elements include fundamental devices, such as gates and flip-flops. The top hierarchical level of the design (often referred to as the “parent”) defines the interconnection of complex logic elements, each of which is made up of elements defined at intermediate hierarchical levels. When elements are used at higher levels in a hierarchical design, their internal structure is not visible—they are treated as “black boxes.” The hierarchical approach thus simplifies the design process, since the designer must contend only with the complexity within a single hierarchical level.
Circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to design and lay out electronic circuits, including simulating the operation of the circuit, determining where cells (i.e., logic elements including devices, e.g., transistors) should be placed and where the interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit and simulate its performance using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern ICs, particularly very-large-scale integrated circuits (VLSICs). For this reason, EDA tools are in wide use.
One such EDA tool performs timing signoff. Timing signoff is one of the last steps in the IC design process and ensures that signal propagation speed (i.e., delay) in a newly-designed circuit is such that the circuit will operate as intended. Signals that propagate too slowly through the circuit cause setup violations; signals that propagate too quickly through the circuit cause hold violations. Setup or hold violations frustrate the logic of the circuit and prevent it from performing the job it was designed to do.